1. Field of the Invention
This invention relates to a method of managing a memory used in a computer, and more particularly, to a method of reducing power consumption of a memory.
2. Related Background Art
With the recent improvement of performance of computer systems, power consumption of the computer systems is on the increase. In particular, a petaflops-class computer in the future has a significant problem with the scale of power consumption of a computer system. In general, in a computer system, power consumption of CPUs, power consumption of memories, and power consumption of other sections are considered to be substantially equal. In order to reduce power consumption of the computer system, dynamic power control for the CPUs is actively performed. However, reduction of power consumption of the memories is rarely examined.
It is possible to set a DRAM used as a main memory for a computer in a low power consumption mode (e.g., a self refresh mode) when there is no memory access. Power consumption of the DRAM set in the low power consumption mode is much lower than that in the normal standby mode. Therefore, it is possible to reduce power consumption of the memories and finally reduce power consumption of the computer system by controlling a power supply mode of the DRAM.
In order to reduce power consumption of the memories, for example, U.S. Pat. No. 6,954,837 discloses a technique for gathering used areas of memories in an arbitrary memory device and setting a memory device not in use in a low power consumption mode.
U.S. Pat. No. 6,215,714 discloses a device that holds data by periodically refreshing only a memory bank that has data.
JP 09-212416 A discloses a technique that includes means for judging whether an entire memory bank is an unused space and memory power saving means and is used for cutting power supply to the memory bank, the entire space of which is an unused space.
On the other hand, in order to reduce power consumption of a processor, for example, JP 2005-235203 A discloses a technique for detecting a command for operating an arithmetic circuit in advance and activating the arithmetic circuit corresponding to the command in advance. After an arithmetic operation is finished, the arithmetic circuit used is inactivated. According to this technique, it is possible to realize reduction in power consumption of a computer system by using a low power consumption mode while controlling latency.